1. Field of the Invention
The present invention relates in general to the design and use of computer system memory. In one aspect, the present invention relates to pseudo random bit stream generators and methods for operating same.
2. Description of the Related Art
Whether integrated as discrete components or in System-on-a-Chip (SoC) applications, memory subsystems (such as double data rate (DDR) synchronous dynamic random access memory (SDRAM)) require precise timing and testing to ensure proper operation, especially as processor and DRAM speeds increase. For example, topological, electrical, thermal, power consumption and/or other environmental factors affecting the delivery of memory data/signals may require adjustment of local sampling clocks to sample in the middle of the received data eye. To make such adjustments, the memory controllers may be trained under BIOS control by sending data patterns from the controller to DRAM and looking for edges in data transitions to identify a “data eye” region where sampling decisions can be made so as to reduce the probability of sampling the incorrect state of the data. Even so, for channels with significant high frequency loss or reflections, data eye closure can arise from the effect of inter-symbol interference (ISI) which becomes more significant as data rates increase. However, as memory speeds increase, BIOS controlled training programs have increased difficulty generating, checking and controlling the training pattern sequences needed to achieve optimal data eye positioning. While hardware training mechanisms placed close to the DDR physical layer can provide good control precision, such solutions typically use a fixed function linear feedback shift register (LFSR) circuits to generate random data patterns. Such hardware circuits have limited flexibility and require significant circuit area, especially as the number of PRBS generator circuits increases with the number of DRAM data lanes.
Accordingly, a need exists for an improved system architecture, design, and method of operation for generating pseudo random data patterns which address various problems in the art that have been discovered by the above-named inventors where various limitations and disadvantages of conventional solutions and technologies will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow, though it should be understood that this description of the related art section is not intended to serve as an admission that the described subject matter is prior art.